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january 2011 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 fsez1317a ? primary-side-regulation pwm with power mosfet integrated fsez1317a primary-side-regulation pwm with power mosfet integrated features ? low standby power under 30mw ? high-voltage startup ? fewest external component counts ? constant-voltage (cv) and constant-current (cc) control without secondary-feedback circuitry ? green-mode: linearly decreasing pwm frequency ? fixed pwm frequency at 50khz with frequency hopping to solve emi problem ? cable compensation in cv mode ? peak-current-mode control in cv mode ? cycle-by-cycle current limiting ? v dd over-voltage protection with auto restart ? v dd under-voltage lockout (uvlo) ? gate output maximum voltage clamped at 15v ? fixed over-temperature protection with auto restart ? available in the 7-lead sop package applications ? battery chargers for cellular phones, cordless phones, pda, digital cameras, power tools, etc. ? replaces linear transformers and rcc smps description this third-generation primary-side-regulation (psr) and highly integrated pwm controller provides several features to enhance the performance of low-power flyback converters. the proprietary topology, truecurrent ? , of fsez1317a enables precise cc regulation and simplified circuit design for battery- charger applications. a low-cost, smaller, and lighter charger results, as compared to a conventional design or a linear transformer. to minimize standby power consumption, the proprietary green mode provides off-time modulation to linearly decrease pwm frequency under light-load conditions. green mode assists the power supply in meeting power conservation requirements. by using the fsez1317a, a charger can be implemented with few external components and minimized cost. a typical output cv/cc characteristic envelope is shown in figure 1. figure 1. typical output v-i characteristic ordering information part number operating temperature range package packing method fsez1317amy_f116 -40c to +105c 7-lead, small outline package (sop-7) tape & reel
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 2 fsez1317a ? primary-side -regulation pwm with power mosfet integrated application diagram d 1 d 3 d 4 d 2 c 1 r sn2 c sn d sn d f c o1 ac input r f dc output l 1 c 2 r sn1 5 8 1 4 vs drain cs comr vdd hv gnd 2 7 3 t 1 d fa c vdd r 1 r 2 c vs r sense c cr c sn2 r sn c o2 r d figure 2. typical application internal block diagram figure 3. functional block diagram
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 3 fsez1317a ? primary-side -regulation pwm with power mosfet integrated marking information figure 4. top mark pin configuration figure 5. pin configuration pin definitions pin # name description 1 cs current sense . this pin connects a current-sense resistor, to detect the mosfet current for peak-current-mode control in cv mode, and provides the output-current regulation in cc mode. 2 vdd power supply . ic operating current and mosfet drivi ng current are supplied using this pin. this pin is connected to an external v dd capacitor of typically 10f. the threshold voltages for startup and turn-off are 16v and 5v, respectively . the operating current is lower than 5ma. 3 gnd ground 4 comr cable compensation . this pin connects a 1f capacitor between the comr and gnd pins for compensation voltage drop due to output cable loss in cv mode. 5 vs voltage sense . this pin detects the output voltage information and discharge time based on voltage of auxiliary winding. 7 hv high voltage . this pin connects to bulk capa citor for high-voltage startup. 8 drain driver output . power mosfet drain. this pin is t he high-voltage power mosfet drain. f : fairchild logo z: plant code x: 1-digit year code y: 1-digit week code tt: 2-digit die run code t: package type (m=sop) p: y=green package m: manufacture flow code
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 4 fsez1317a ? primary-side -regulation pwm with power mosfet integrated absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v hv hv pin input voltage 500 v v vdd dc supply voltage (1,2) 30 v v vs vs pin input voltage -0.3 7.0 v v cs cs pin input voltage -0.3 7.0 v v comv voltage error amplifier output voltage -0.3 7.0 v v comi current error amplifier ou tput voltage -0.3 7.0 v v ds drain-source voltage 700 v i d continuous drain current t a =25c 1 a t a =100c 0.6 a i dm pulsed drain current 4 a e as single pulse avalanche energy 50 mj i ar avalanche current 1 a p d power dissipation (t a 50c) 660 mw ja thermal resistance (junction-to-air) 150 c/w jt thermal resistance (junction-to-case) 39 c/w t j operating junction temperature -40 +150 c t stg storage temperature range -55 +150 c t l lead temperature (wave soldering or ir, 10 seconds) +260 c esd electrostatic discharge capability (except hv pin) human body model, jedec-jesd22_a114 5000 v charged device model, jedec-jesd22_c101 2000 notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential volt ages, are given with respect to the gnd pin. 3. esd ratings including hv pin: hbm=500v, cdm=1250v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensur e optimal performance to the datasheet specificati ons. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units t a operating ambient tem perature -40 +105 c
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 5 fsez1317a ? primary-side -regulation pwm with power mosfet integrated electrical characteristics unless otherwise specified, v dd =15v and t a =25 . symbol parameter conditions min. typ. max. units v dd section v op continuously operating voltage 23 v v dd-on turn-on threshold voltage 15 16 17 v v dd-off turn-off threshold vo ltage 4.5 5.0 5.5 v i dd-op operating current 2.5 5.0 ma i dd-green green-mode operating supply current 0.95 1.45 ma v dd-ovp v dd over-voltage-protection level (ovp) 24 v v dd-ovp-hys hysteresis voltage for v dd ovp 1.5 2.0 2.5 v t d-vddovp v dd over-voltage-protection debounce time 50 200 300 s hv startup current source section v hv-min minimum startup voltage on hv pin 50 v i hv supply current drawn from hv pin v dc =100v 1.5 3.0 ma i hv-lc leakage current after startup hv=500v, v dd = v dd- off +1v 0.96 3.00 a oscillator section f osc frequency center frequency 47 50 53 khz frequency hopping range 3.5 f osc-n-min minimum frequency at no-load 370 hz f osc-cm-min minimum frequency at ccm 13 khz f dv frequency variation vs. v dd deviation v dd =10~25v, 1 2 % f dt frequency variation vs. temperature deviation t a =-40c to 105c 15 % voltage-sense section i tc ic bias current 10 a v bias-comv adaptive bias voltage dominated by v comv r vs =20k ? 1.4 v current-sense section t pd propagation delay to gate output 90 200 ns t min-n minimum on time at no-load 600 725 950 ns v th threshold voltage for current limit 0.8 v voltage-error-am plifier section v vr reference voltage 2.475 2.500 2.525 v v n green-mode starting voltage on ea_v f osc -5khz 2.2 v v g green-mode ending voltage on ea_v f osc =1khz 0.4 v current-error-amplifier section v ir reference voltage 2.475 2.500 2.525 v cable compensation section v comr comr pin for cable compensation 0.85 v continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 6 fsez1317a ? primary-side -regulation pwm with power mosfet integrated electrical characteristics (continued) unless otherwise specified, v dd =15v and t a =25 . symbol parameter conditions min. typ. max. units internal mosfet section (4) dcy max maximum duty cycle 52 65 78 % bv dss drain-source breakdown voltage i d =250 a, v gs =0v 700 v ? bv dss / ? t j breakdown voltage temperature coefficient i d =250 a, referenced to t a =25c 0.53 v/c r ds(on) static drain-source on-resistance i d =0.5a, v gs =10v 13 16 ? i s maximum continuous drain-source diode forward current 1 a i dss drain-source leakage current v ds =700v, t a =25c 10 a v ds =560v, t a =100c 100 a t d-on turn-on delay time v ds =350v, i d =1a, r g =25 ? (5) 10 30 ns t d-off turn-off delay time 20 50 ns c iss input capacitance v gs =0v, v ds =25v, f s =1mhz 175 200 pf c oss output capacitance 23 25 pf over-temperature-protection section t otp threshold temperature for otp (6) +140 c notes: 4. these parameters, alt hough guaranteed, are not 100% tested in production. 5. pulse test: pulsewidth Q 300s, duty cycle Q 2%. 6. when the over-temperature protection is activated, the power syst em enter auto-restart mode and output is disabled.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 7 fsez1317a ? primary-side -regulation pwm with power mosfet integrated typical performance characteristic s 15 15.4 15.8 16.2 16.6 17 -40 -30 -15 0 25 50 75 85 100 125 v dd_on (v) temperature (oc) 4.5 4.7 4.9 5.1 5.3 5.5 -40 -30 -15 0 25 50 75 85 100 125 v dd_off (v) temperature (oc) figure 6. turn-on threshold voltage (v dd-on ) vs. temperature figure 7. turn-off threshold voltage (v dd-off ) vs. temperature 1 1.8 2.6 3.4 4.2 5 -40 -30 -15 0 25 50 75 85 100 125 i dd_op (ma) temperature (oc) 42 45 48 51 54 -40 -30 -15 0 25 50 75 85 100 125 f osc (khz) temperature (oc) figure 8. operating current (i dd-op ) vs. temperature figure 9. center frequency ( f osc ) vs. temperature 2.465 2.475 2.485 2.495 2.505 2.515 2.525 -40 -30 -15 0 25 50 75 85 100 125 v vr (v) temperature (oc) 0.8 0.84 0.88 0.92 0.96 1 -40 -30 -15 0 25 50 75 85 100 125 i dd_green (ma) temperature (oc) figure 10. reference voltage (v vr ) vs. temperature figure 11. green mode operating supply current (i dd-green ) vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 8 fsez1317a ? primary-side -regulation pwm with power mosfet integrated typical performance characteristics (continued) 330 350 370 390 410 430 450 -40 -30 -15 0 25 50 75 85 100 125 f osc_green (hz) temperature (oc) 10 11 12 13 14 15 16 -40 -30 -15 0 25 50 75 85 100 125 f osc_cm_min (khz) temperature (oc) figure 12. minimum frequency at no load (f osc-n-min ) vs. temperature figure 13. minimum frequency at ccm ( f osc-cm-min ) vs. temperature 0 0.5 1 1.5 2 2.5 3 -40 -30 -15 0 25 50 75 85 100 125 i hv (v) temperature (oc) 400 500 600 700 800 900 1000 -40 -30 -15 0 25 50 75 85 100 125 t min_n (v) temperature (oc) figure 14. supply current drawn from hv pin (i hv ) vs. temperature figure 15. minimum on time at no load (t min-n ) vs. temperature 2.3 2.335 2.37 2.405 2.44 2.475 -40 -30 -15 0 25 50 75 85 100 125 v n (v) temperature (oc) 0.3 0.317 0.334 0.351 0.368 0.385 -40 -30 -15 0 25 50 75 85 100 125 v g (v) temperature (oc) figure 16. green mode starting voltage on ea _ v (v n ) vs. temperature figure 17. green mode ending voltage on ea _ v (v g ) vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 9 fsez1317a ? primary-side -regulation pwm with power mosfet integrated typical performance characteristics (continued) 8.6 8.8 9 9.2 9.4 9.6 9.8 -40 -30 -15 0 25 50 75 85 100 125 i tc (ua) temperature (oc) 1 1.1 1.2 1.3 1.4 1.5 1.6 -40 -30 -15 0 25 50 75 85 100 125 v bias_comv (v) temperature (oc) figure 18. ic bias current (i tc ) vs. temperature figure 19. a daptive bias v oltage dominated by v comv (v bias-comv ) vs. temperature 0.78 0.79 0.8 0.81 0.82 0.83 0.84 -40 -30 -15 0 25 50 75 85 100 125 v th_vs0.6v (ns) temperature (oc) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -40 -30 -15 0 25 50 75 85 100 125 i hv_lc (ma) temperature (oc) figure 20. threshold voltage for current limit ( v th ) vs. temperature figure 21. leakage current after startup (i hv-lc ) vs. temperature 0.79 0.81 0.83 0.85 0.87 0.89 0.91 -40 -30 -15 0 25 50 75 85 100 125 v comr (v) temperature (oc) 64 66 68 70 72 74 76 -40 -30 -15 0 25 50 75 85 100 125 dcy max (%) temperature (oc) figure 22. v ariation test voltage on comr pin for cable compensation (v comr ) vs. temperature figure 23. maximum duty cycle (dcy max ) vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 10 fsez1317a ? primary-side -regulation pwm with power mosfet integrated functional description figure 24 shows the basic circuit diagram of primary- side regulated flyback converter, with typical waveforms shown in figure 25. generally, discontinuous conduction mode (dcm) operation is preferred for primary-side regulation because it allows better output regulation. the operation principles of dcm flyback converter are as follows: during the mosfet on time (t on ), input voltage (v dl ) is applied across the primary-side inductor (l m ). then mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor. when the mosfet is turned off, the energy stored in the inductor forces the rectifier diode (d) to be turned on. while the diode is cond ucting, the output voltage (v o ), together with diode forward-voltage drop (v f ), is applied across the secondary-side inductor ( l m ? n s 2 / n p 2 ) and the diode current (i d ) decreases linearly from the peak value (i pk ? n p /n s ) to zero. at the end of inductor current discharge time (t dis ), all the energy stored in the inductor has been delivered to the output. when the diode current reaches zero, the transformer auxiliary winding voltage (v w ) begins to oscillate by the resonance between the primary-side inductor (l m ) and the effective capacitor l oaded across the mosfet. during the inductor current discharge time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (v o +v f ) ? n a /n s . since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltag e best at the end of diode conduction time where the diode current diminishes to zero. thus, by sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. the internal error amplifier for output voltage regulation (ea_v) compares the sampled voltage with internal precise reference to generate error voltage (v comv ), which determines the duty cycle of the mosfet in cv mode. meanwhile, the output curre nt can be estimated using the peak drain current and inductor current discharge time because output current is same as the average of the diode current in steady state. the output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output curr ent using the inductor discharge time (t dis ) and switching period (t s ). this output information is compared with internal precise reference to generate error voltage (v comi ), which determines the duty cycle of the mosfet in cc mode. with fairchild?s innovative technique truecurrent ? , constant current (cc) ou tput can be precisely controlled. among the two error voltages, v comv and v comi , the smaller one determines the duty cycle. therefore, during constant voltage regulation mode, v comv determines the duty cycle while v comi is saturated to high. during constant current regulation mode, v comi determines the duty cycle while v comv is saturated to high. + v dl - l m + v o - n p :n s i ds i d d primary-side regulation controller + v w - v dd v s cs +v f - n a l o a d i o i o estimator v o estimator t dis detector pwm control r cs v ac ref ref ea_v ea_i v comv v comi r s1 r s2 figure 24. simplified psr flyback converter circuit p pk s n i n ? . d avg o i i ? ? ? figure 25. key waveforms of dcm flyback converter
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 11 fsez1317a ? primary-side-regulation pwm with power mosfet integrated cable voltage drop compensation in cellular phone charger applications, the battery is located at the end of cable, which typically causes several percentage of voltage drop on the battery voltage. fsez1317a has a bu ilt-in cable voltage drop compensation that provides a constant output voltage at the end of the cable over th e entire load range in cv mode. as load increases, the voltage drop across the cable is compensated by increasing the reference voltage of the voltage r egulation error amplifier. operating current the fsez1317a operating current is as small as 2.5ma, which results in higher efficiency and reduces the v dd hold-up capacitance requirement. once fsez1317a enters ?deep? green mode, the operating current is reduced to 0.95ma, assisting the power supply in meeting power conservation requirements. green-mode operation the fsez1317a uses voltage regulation error amplifier output (v comv ) as an indicator of the output load and modulates the pwm frequency as shown in figure 26. the switching frequency decreases as the load decreases. in heavy load conditions, the switching frequency is fixed at 50khz. once v comv decreases below 2.5v, the pwm frequency linearly decreases from 50khz. when fsez1317a enters deep green mode, the pwm frequency is reduced to a minimum frequency of 370hz, thus gaining power saving to meet international power conservation requirements. figure 26. switching frequency in green mode frequency hopping emi reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the emi test equipment. fsez1317a has an internal frequency hopping circuit that c hanges the switching frequency between 46khz and 54khz over the period shown in figure 27. figure 27. frequency hopping high-voltage startup figure 28 shows the hv-startup circuit for fsez1317a applications. the hv pin is c onnected to the line input or bulk capacitor through a resistor, r start (100k ? recommended). during startup status, the internal startup circuit is enabled. meanwhile, line input supplies the current, i startup , to charge the hold-up capacitor, c dd , through r start . when the v dd voltage reaches v dd-on , the internal startup circ uit is disabled, blocking i startup from flowing into the hv pin. once the ic turns on, c dd is the only energy source to supply the ic consumption current before t he pwm starts to switch. thus, c dd must be large enough to prevent v dd from dropping down to v dd-off before the power can be delivered from the auxiliary winding. figure 28. hv startup circuit
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 12 fsez1317a ? primary-side-regulation pwm with power mosfet integrated under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 16v and 5v, respectively. during startup, the hold-up capacitor must be charged to 16v through the startup resistor to enable the fsez1317a. the hold-up capacitor continues to supply v dd until power can be delivered from the auxiliary winding of the main transformer. v dd is not allowed to drop below 5v during this startup process. this uvlo hysteresis window ensures that hold-up capacitor properly supplies v dd during startup. protections the fsez1317a has several self-protection functions, such as over-voltage protection (ovp), over- temperature protection (otp), and pulse-by-pulse current limit. all the protec tions are implemented as auto-restart mode. once the abnormal condition occurs, the switching is terminated and the mosfet remains off, causing v dd to drop. when v dd drops to the v dd turn-off voltage of 5v, internal startup circuit is enabled again and the supply current drawn from the hv pin charges the hold-up capacitor. when v dd reaches the turn-on voltage of 16v, normal operation resumes. in this manner, the auto-restar t alternately enables and disables the switching of the mosfet until the abnormal condition is eliminated (see figure 29). figure 29. auto-restart operation v dd over-voltage protection (ovp) v dd over-voltage protection prevents damage from over- voltage conditions. if the v dd voltage exceeds 24v at open-loop feedback condition, ovp is triggered and the pwm switching is disabled. the ovp has a debounce time (typically 200s) to prevent false triggering due to switching noises. over-temperature protection (otp) the built-in temperature-sensing circuit shuts down pwm output if the junction temperature exceeds 140c. pulse-by-pulse current limit when the sensing voltage across the current-sense resistor exceeds the internal threshold of 0.8v, the mosfet is turned off for the remainder of switching cycle. in normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop. leading-edge blanking (leb) each time the power mosfet switches on, a turn-on spike occurs at the sense re sistor. to avoid premature termination of the switching pulse, a leading-edge blanking time is built in. during this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. as a result conventional rc filtering can be omitted. gate output the fsez1317a output stage is a fast totem-pole gate driver. cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 15v zener diode to protect the power mosfet transistors against undesired over-voltage gate signals. built-in slope compensation the sensed voltage across the current-sense resistor is used for current mode control and pulse-by-pulse current limiting. built-in slope compensation improves stability and prevents sub-harm onic oscillations due to peak-current mode control. the fsez1317a has a synchronized, positive-slope ramp built-in at each switching cycle. noise immunity noise from the current sens e or the control signal can cause significant pulsewidth jitter, particularly in continuous-conduction mode. while slope compensation helps alleviate these problems, further precautions should still be taken. good placement and layout practices should be followed. avoiding long pcb traces and component leads, locating compensation and filter components ne ar the fsez1317a, and increasing the power mos gate resistance are advised.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 13 fsez1317a ? primary-side -regulation pwm with power mosfet integrated typical application circuit (primary -side regulated flyback charger) application fairchild devices input voltage range output output dc cable cell phone charger fsez1317a 90~265v ac 5v/0.7a (3.5w) awg26, 1.8 meter features ? high efficiency (>65.5% at full load) meet ing eps 2.0 regulation with enough margin ? low standby (pin<30mw at no-load condition) figure 30. measured efficiency figure 31. standby powe r figure 32. schematic of typical application circuit
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 14 fsez1317a ? primary-side-regulation pwm wi th power mosfet integrated typical application circuit (continued) transformer specification ? core: ee16 ? bobbin: ee16 figure 33. transformer specification notes: 7. when w4r?s winding is reversed wi nding, it must wind one layer. 8. when w2 is winding, it must wind three layers and put one layer of tape after winding the first layer. no. terminal wire t s insulation barrier tape s f t s primary seconds w1 4 5 2uew 0.23*2 15 2 w2 3 1 2uew 0.17*1 41 1 39 0 37 2 w3 1 copper shield 1.2 3 w4 7 9 tex-e 0.55*1 9 3 core rounding tape 3 pin specification remark primary-side inductance 1 3 2.25mh 7% 100khz, 1v primary-side effective leakage 1 3 80 ? h 5% short one of the secondary windings 5 4 bobbin 3 1 1 9 7 auxiliary winding primary winding 1st shield secondary winding
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 15 fsez1317a ? primary-side-regulation pwm wi th power mosfet integrated physical dimensions figure 34. 7-lead, small outline package (sop-7) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fsez1317a ? rev. 1.0.1 16 fsez1317a ? primary-side-regulation pwm wi th power mosfet integrated

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